MIPS: mips32/cache.S: use v1 register for indirect function calls

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index d3f156e4822a908738e9e96cdc793a937506b249..12f656cad0a7746f1cbcb2c56a3238f04c67c198 100644 (file)
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -156,16 +156,16 @@ NESTED(mips_cache_reset, 0, ra)
         */
        move    a1, t2
        move    a2, t8
-       PTR_LA  t7, mips_init_icache
-       jalr    t7
+       PTR_LA  v1, mips_init_icache
+       jalr    v1
 
        /*
         * then initialize D-cache.
         */
        move    a1, t3
        move    a2, t8
-       PTR_LA  t7, mips_init_dcache
-       jalr    t7
+       PTR_LA  v1, mips_init_dcache
+       jalr    v1
 
        jr      RA
        END(mips_cache_reset)